作者


xiaoyisimonguo
用户组: -
开通时间:-
更新时间:-
上次登录时间:-
How to find the library features

I am running synthesis in DC with loaded a few library DB's: Loading db file '/home/dubeeloo/proj/DFTcompiler/DFTorTiming/sc_max.db' Loading db file '/home/dubeeloo/proj/DFTcompiler/DFTorTiming/i...

点击此处查看原文 2017-07-03 | 评论(2) | 阅读(201)

breaking timing loop

I useddisable_timing {I_CLOCK_GEN/I_PLL_SD/FB_CLK I_CLOCK_GEN/I_PLL_SD/CLK} to break the timing loop in DC: END-> I_CLOCK_GEN/U3/B1(aor22d1) I_CLOCK_GEN/net_sdram_clk ...

点击此处查看原文 2017-07-02 | 评论(1) | 阅读(317)

fix warning

Warning: Gated clock latch is not created for cell 'I_CLOCK_GEN/U6/*cell*13737'on pin 'I0' I am not sure if we need to fix All the warnings Please help how could I I fix the warning?

点击此处查看原文 2017-07-01 | 评论(0) | 阅读(210)

how to break a timing loop

I got the information saying timng loop detected: nformation: Timing loop detected. (OPT-150) I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/REG_FILE_A_RAM_1/OEB1 I_ORCA_TOP/I_RISC_CORE/I_REG_FILE/REG_FILE_A_R...

点击此处查看原文 2017-07-01 | 评论(3) | 阅读(112)

help on DC timing violation

DC reported a -1,18 slack of setup violation:the data arrive path is like this: I_ORCA_TOP/I_SDRAM_IF/sd_DQ_en (SDRAM_IF_sd_a_width10_sd_dq_width16) 0.00 0.34 r I_ORCA_TOP/I_SDRAM...

点击此处查看原文 2017-06-30 | 评论(1) | 阅读(149)

help on DC timing violation

DC reported a -1,18 slack of setup violation:the data arrive path is like this: I_ORCA_TOP/I_SDRAM_IF/sd_DQ_en (SDRAM_IF_sd_a_width10_sd_dq_width16) 0.00 0.34 r I_ORCA_TOP/I_SDRAM...

点击此处查看原文 2017-06-30 | 评论(0) | 阅读(122)

help on DC timing violation

DC reported a -1,18 slack of setup violation:the data arrive path is like this: I_ORCA_TOP/I_SDRAM_IF/sd_DQ_en (SDRAM_IF_sd_a_width10_sd_dq_width16) 0.00 0.34 r I_ORCA_TOP/I_SDRAM...

点击此处查看原文 2017-06-30 | 评论(0) | 阅读(92)

tech file and tluplus

this web page talked about tf and tluplus extraction differences http://www.edaboard.com/thread259143.html tf, milkyway.tf is for P&R tluplus files for extraction both could be used in ICC/...

点击此处查看原文 2017-06-30 | 评论(1) | 阅读(119)

VHDL coding examples

please check out the VHDL coding examples: 694660

点击此处查看原文 2017-06-30 | 评论(0) | 阅读(83)

VHDL coding examples

check out the following examples of VHDL coding http://vhdlguru.blogspot.com/p/example-codes.html

点击此处查看原文 2017-06-30 | 评论(0) | 阅读(62)

for VHDL coding

Please check out the following web for VHDL coding examples http://vhdlguru.blogspot.com/p/example-codes.html

点击此处查看原文 2017-06-30 | 评论(0) | 阅读(171)

good examples for VHDL coding

please check out the follow web http://vhdlguru.blogspot.com/p/example-codes.html

点击此处查看原文 2017-06-30 | 评论(0) | 阅读(80)

VHDL coding cookbook

for those of us need to code VHDL, please check out this cookbook 694639

点击此处查看原文 2017-06-29 | 评论(6) | 阅读(221)

help on DFT flow

need help I using DFT labs DFTCompilerêμÑéÅàÑμ×êáÏ the lab have two flows unmapped and mapped I did run them both. According to lab instruction *Lab.pdf all the ...

点击此处查看原文 2017-06-29 | 评论(3) | 阅读(233)

please help for VHDL code

I don't have much VHDL coding experience, please help for the follow code IO1 port is defined in component section port( ... ... IO1 : inout std_logic_vector(31 downto 0); ... ); at th...

点击此处查看原文 2017-06-28 | 评论(1) | 阅读(153)

help tcl cammands

when I ran DC or ICC, sometime I got set-up violationby studying the violation report, I know if I swap a few cells from hvt cells to lvt cells I could easily fix the violations. But how? in D...

点击此处查看原文 2017-06-26 | 评论(1) | 阅读(99)

how to change VHDL code to get rid of latch's

please help, I need to change the following code to get rid of the latch synthesized clk_en_latch: PROCESS(clk_enable, clk) BEGIN IF clk = '0' THEN latched_clk_en

点击此处查看原文 2017-06-25 | 评论(0) | 阅读(93)

can run cadence license

still could not run cadence tools like EDI and virtuoso, please help Here are the license daemon log: 23:03:39 (lmgrd) World Wide Web: http://www.macrovision.com 23:03:39 (lmgrd) License file...

点击此处查看原文 2017-06-23 | 评论(1) | 阅读(77)

how to create timing constraint files, please help

How to generate timing constraint files for design compiler.Does DC have an automated way to do that by applying some of the default constraints. Otherwise, there are a lots pins to deal, most o...

点击此处查看原文 2017-06-23 | 评论(1) | 阅读(103)

help to fix setup violation in DC or ICC

when I ran DC or ICC, sometime I got set-up violationby studying the violation report, I know if I swap a few cells from hvt cells to lvt cells I could easily fix the violations. But how...

点击此处查看原文 2017-06-23 | 评论(0) | 阅读(255)

UCenter info: MySQL Query Error
SQL:SELECT * FROM [Table]notelist WHERE closed='0' AND app5<'1' AND app5>'-5' LIMIT 1
Error:Unknown column 'app5' in 'where clause'
Errno:1054