Implementing Memory Structures for Video Processing in the Vivado HLS Tool

This application note describes the main considerations when implementing an image or video
processing algorithm with the Vivado™ High-Level Synthesis (HLS) tool. These kinds of
algorithms, which are predominantly computation intensive, are natural candidates for
hardware implementation with the HLS tool. The techniques described in this application note
cover the basics of video algorithm implementation in the HLS tool in terms of synchronization
signal handling and memory architectures. Regardless of the exact computation in the user
algorithm, these types of applications are memory intensive. The memory architecture
expressed in the algorithm has a direct correlation to overall system performance and hardware
resource consumption. The recommendations on memory buffer architecture presented in this
application note are applicable to Vivado HLS designs on all Xilinx FPGAs.