FPGA IP的挑战是哪些？

In this column, I'm continuing a mini-series on the development of Intellectual Property (IP) cores from FPGA suppliers.

In my previous article, I covered the history of the evolution of IP cores over the last several years based on a discussion with Tim Vanevenhoven, Director of Marketing, IP Design Methodology at Xilinx. Tim has many years of experience developing IP and the associated tools, methodologies, and strategies used within Xilinx. We continue our discussion on current challenges in today's post and -- in particular -- we consider how the new Xilinx Vivado Design Suite approaches these challenges.

IP grows up
As we discussed previously, Tim explained that the development of robust IP cores held out the promise of increased productivity to designers. As FPGA capacity skyrocketed, it became critical to provide large chunks of the design that were "already done," or designers would spend too much time filling the capacity of these new devices "by hand."

The idea was that IP blocks that provide common functions could be used to quickly build up the "standard" portions of the design (interfaces, memory, FIFO, arithmetic functions, etc.). This would leave the designers free to focus on creating new and differentiated algorithms as the way to provide value to their customers. Unfortunately, the growth in the demand for IP blocks outstripped the FPGA suppliers' ability to create robust IP environments. The result was that users needed to spend so much time adapting the IP for their design (adding glue logic, fighting with incompatible design and verification flows, etc.) that the promised productivity improvements were significantly diminished.

The response to the challenges discussed in last week's blog required a significantly different approach to thinking about, and supporting, IP cores. At Xilinx, this approach was embodied in the development of a new generation of software -- the Xilinx Vivado Design Suite.

Introduced in April 2012 (click here to see Max's blog on this launch) after four years of development and a year of beta testing, the IP and system-centric Vivado Design Suite was created from the ground up to accelerate design productivity for the next decade of Xilinx's All Programmable FPGAs, DoCs, and 3D ICs. Tim explained how some of the specific features of Vivado address the key IP-related challenges presented in last week's blog.

Difficulty in integrating IP cores
One of the most time consuming aspects of using IP cores was the difficulty in integrating multiple cores into a single design. Interfaces were not consistent, there were multiple catalogs of IP to select from, and even the meta-data used to describe the "contents" of an IP core were inconsistent.

The folks at Xilinx used the Vivado development to put IP cores central to the design flow. They also used a variety of industry standards to significantly improve the designers' productivity. Some examples of standards supported in Vivado are as follows:

• A consistent set of IP blocks with a common interface (the AMBA AXI4 ARM standard for defining IP interconnect)
• A consistent meta-data format (the IP-XACT IEEE Std 1685-2009 XML format for component definition)
• A common library model (Liberty Modeling Library- .lib).

These may seem like "no brainers" now, but it required a significant investment to take legacy IP and migrate it to these new standards. However, this was an investment that is sure to pay off significantly in improved productivity.

Difficulty in managing IP collections
Another issue FPGA manufacturers faced was the difficulty designers had in understanding, organizing, and managing the collections (catalogs) of IP from the FPGA vendors, third-party IP providers, and company-internal IP groups.

The various pieces of the IP puzzle seldom used the same approach to organize IP cores. Once IP cores were using a common set of standards, it became possible to create an IP catalog that could easily have new elements added as the designer needed. The "IP Packager" uses IP-XACT to package an IP core complete with constraints, test benches, and documentation into an IP Catalog.

The IP Packager uses a customized parameterization GUI to simplify adding any IP core to the user's catalog (FPGA manufacturer, third-party, or company-internal) and -- with the security provided by encrypted IEEE P1735 design files -- simplifies all aspects of the design flow, independent of the source of the IP. In turn, this significantly simplifies the process of integration of IP from a variety of sources into a single design.

Difficulty in connecting IP blocks
One of the primary sources of frustration in implementing large designs was the need to "glue" together IP blocks with different interfaces or slightly different signal characteristics (signal polarity, latency, etc.). The use of RTL "shims" and "gaskets" were typically required, and these reduced design, verification, and test productivity. With the standardization on a common interface and the availability of better, common metadata, it is possible to construct a much more productive design flow.

Xilinx created an IP Integrator as a feature of Vivado that will make it much easier to combine IP blocks into a single design. IP Integrator enables the user to build and verify a hierarchical system by graphically connecting IP provided by Xilinx, third-parties, or the developer's propriety IP. This "one-click" approach to connecting and verifying multiple block designs guarantees that the system design is structurally correct by construction. The design itself can then be packaged and placed in the Vivado IP catalog for later reuse. This approach can dramatically increase designer productivity when creating a system using multiple IP core blocks.

These are just a few of the Xilinx responses to the challenges faced when designing with IP cores that are included in the Vivado software from Xilinx. Every FPGA manufacturer is facing a similar set of challenges and will have their own responses, but one thing is common -- the need to dramatically improve designer productivity. Do you have any insight into how other FPGA manufacturers are responding? Please add your comments to this post and let us know!

Even with the challenges addressed as discussed here, new issues are just over the horizon. So don't forget to tune in next week when we move on to consider the future of IP cores for FPGAs and we look at the set of new challenges that are just over the horizon.