在ZC702上运行Linux(1) - 运行Pre-built images

Xilinx针对ZC702提供了Linux Porting。

参考文档在http://wiki.xilinx.com/

源码在http://git.xilinx.com/

拿到板子的第一步当然是先跑一下Pre-built images看看，一者可以验证板子好坏，再者可以看看Linux已经完成了那些功能，做到了哪一步。毕竟，站在巨人的肩膀上才能看的更高，走的更远。

最新的Pre-built images在http://wiki.xilinx.com/zynq-release-14-3

拷贝以下文件到SD卡上，SW16配置成00110，就可以在ZC702上启动Linux了。

BOOT.BIN

devicetree.dtb

uImage

uramdisk.image.gz

串口上的输出如下：

U-Boot 2012.04.01-00304-g7639205 (Oct 23 2012 - 08:29:31)

DRAM:  1 GiB

WARNING: Caches not enabled

MMC:   SDHCI: 0

Using default environment

In:    serial

Out:   serial

Err:   serial

Net:   zynq_gem

Hit any key to stop autoboot:  0

Copying Linux from SD to RAM...

Device: SDHCI

Manufacturer ID: 3

OEM: 5344

Name: SU08G

Tran Speed: 25000000

Rd Block Len: 512

SD version 2.0

High Capacity: Yes

Capacity: 7.4 GiB

Bus Width: 4-bit

reading uImage

2725416 bytes read

reading devicetree.dtb

4366 bytes read

reading uramdisk.image.gz

5252253 bytes read

## Booting kernel from Legacy Image at 03000000 ...

   Image Name:   Linux-3.5.0-14.3-build2

   Created:      2012-10-23  18:12:23 UTC

   Image Type:   ARM Linux Kernel Image (uncompressed)

   Data Size:    2725352 Bytes = 2.6 MiB

   Load Address: 00008000

   Entry Point:  00008000

   Verifying Checksum ... OK

## Loading init Ramdisk from Legacy Image at 02000000 ...

   Image Name:

   Created:      2012-10-03  21:10:37 UTC

   Image Type:   ARM Linux RAMDisk Image (gzip compressed)

   Data Size:    5252189 Bytes = 5 MiB

   Load Address: 00800000

   Entry Point:  00800000

   Verifying Checksum ... OK

## Flattened Device Tree blob at 02a00000

   Booting using the fdt blob at 0x02a00000

   Loading Kernel Image ... OK

OK

   Loading Ramdisk to 1fafd000, end 1ffff45d ... OK

   Loading Device Tree to 1faf8000, end 1fafc10d ... OK

Starting kernel ...

Uncompressing Linux... done, booting the kernel.

Booting Linux on physical CPU 0

Linux version 3.5.0-14.3-build2 (linnj@xsjpsgv107) (gcc version 4.6.1 (Sourcery CodeBench Lite 2011.09-50) ) #1 SMP PREEMPT Tue Oct 23 11:12:17 PDT 2012

CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d

CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

Machine: Xilinx Zynq Platform, model: Xilinx Zynq ZC702

bootconsole [earlycon0] enabled

cma: CMA: reserved 16 MiB at 2e800000

Memory policy: ECC disabled, Data cache writealloc

PERCPU: Embedded 7 pages/cpu @c0e2a000 s6784 r8192 d13696 u32768

Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 259840

Kernel command line: console=ttyPS0,115200 root=/dev/ram rw ip=192.168.1.10:::255.255.255.0:ZC702:eth0 earlyprintk

PID hash table entries: 4096 (order: 2, 16384 bytes)

Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)

Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)

Memory: 1024MB = 1024MB total

Memory: 1011624k/1011624k available, 36952k reserved, 270336K highmem

Virtual kernel memory layout:

    vector  : 0xffff0000 - 0xffff1000   (   4 kB)

    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)

    vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)

    lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)

    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)

    modules : 0xbf000000 - 0xbfe00000   (  14 MB)

      .text : 0xc0008000 - 0xc048e060   (4633 kB)

      .init : 0xc048f000 - 0xc04b4a80   ( 151 kB)

      .data : 0xc04b6000 - 0xc04f3c20   ( 248 kB)

       .bss : 0xc04f3c44 - 0xc051f104   ( 174 kB)

Preemptible hierarchical RCU implementation.

        Dump stacks of tasks blocking RCU-preempt GP.

NR_IRQS:128

Zynq clock init

xlnx,ps7-ttc-1.00.a #0 at 0xf0000000, irq=43

sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 4294967286ms

Console: colour dummy device 80x30

Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)

pid_max: default: 32768 minimum: 301

Mount-cache hash table entries: 512

CPU: Testing write buffer coherency: ok

CPU0: thread -1, cpu 0, socket 0, mpidr 80000000

hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available

Setting up static identity map for 0x351160 - 0x351194

L310 cache controller enabled

l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72360000, Cache size: 524288 B

Map SLCR registers

CPU1: Booted secondary processor

CPU1: thread -1, cpu 1, socket 0, mpidr 80000001

Brought up 2 CPUs

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