菜鸟如何搞定高速SerDes端口设计？4分钟教程视频帮你解决难题

菜鸟如何搞定高速SerDes端口设计？4分钟教程视频帮你解决难题

http://forums.xilinx.com/t5/Xcell-Daily-Blog/New-to-Multi-Gbps-SerDes-ports-This-4-minute-tutorial-video-can/ba-p/415221

Multi-Gbps SerDes transceivers started as high-end FPGA features but they’re now pervasive in system design. That’s because they’re just so darn useful in moving a lot of data from here to there in a short amount of time with few connections—when they work. Because they’re so useful, these handy, high-speed I/O ports have even migrated intolow-end programmable logic devices including the Xilinx Zynq All Programmable SoC, Artix-7 FPGAs, and Spartan-6 FPGAs.

速率高达数Gbps的高速SerDes收发器已经开始作为高端FPGA的标配了，但它们大都用在系统设计中。这是因为当它们工作时，它们只靠少数的几个连接在很短时间内就把大量数据从这儿搬到那儿，这简直太有用了。正因为它们是如此有用，这些方便、高速的I/ O端口甚至已经出现在一些低端的可编程器件上，包括赛灵思的Zynq All Programmable SoC、Artix-7 FPGA以及Spartan-6 FPGA。

If you’re new to using and optimizing SerDes ports in your design, this painless 4-minute tutorial on multi-Gbps interconnect challenges is for you. In this video, Martin Gilpatric, Transceiver Technical Marketing Manager at Xilinx, discusses some of the challenges you will experience when developing systems that incorporate multi-Gbps connections. These challenges include channel loss with increasing frequency, stubs and connectors that create impedance perturbations and reflections, and the need to learn new design tools to help you analyze and optimize multi-Gbps connections in your design. The video also gives you a few places to look for more extensive design help.

如果你是一个菜鸟，要在你的设计中使用并优化SerDes端口，那这个关于高速互连挑战的4分钟教程正对你的胃口，在这段视频中，赛灵思收发器技术营销经理Martin Gilpatric讨论了一些在开发数Gbps连接系统时要经历的挑战，这些挑战包括随频率提升、短截线和连接器（会导致阻抗微扰、反射）带来的信道损耗，他也谈到你需要学习什么新的设计工具帮你分析和优化你设计中的高速连接，该视频还为您提供了几个能寻找到更多设计帮助的网址。

Here’s the video:

这是视频

视频: