赛灵思“20nm GTY 30.5Gbps SerDes”开发团队赢得公司 2015 Ross Freeman 硬件类大奖

热烈祝贺赛灵思“20nm GTY 30.5Gbps SerDes”开发团队赢得公司 2015 Ross Freeman 硬件类大奖！ 至于其如何在赛灵思众多的创新中赢得众多全球员工的青睐并在投票中脱颖而出， 请听赛灵思CTO如何说！

Last week, Xilinx CTO and Senior Vice President Ivo Bolsens presented two Ross Freeman Awards for Technical Innovation to the hardware and software innovation teams responsible for developing the relevant technologies. I interviewed Ivo after the awards to get more detail. This blog contains Ivo’s remarks about the hardware award, for the 20nm GTY 30.5Gbps SerDes in Xilinx Virtex UltraScale devices.

Ivo Bolsens:

What we are trying to do with the Ross Freeman Awards for Technical Innovation is recognize technical innovations—the technical contributions—that have reached the market in our products over the last fiscal year. That is, the technology that has reached our customers. These recognized innovations are a major differentiator in our products.

We’ve made these awards 23 times. In the past, there was only one award. Over time, as Xilinx has become more and more a software company, so recently we decided to give one award for hardware innovation and one for software innovation.

Sometimes, the problem you have at Xilinx is that the distinction between hardware and software is blurred because everything is programmable. What is hardware? What is software? You have silicon hardware. You have soft hardware. You have software running on soft hardware (code running on MicroBlaze processors, for example). You have software running on hard hardware (code running on the ARM Cortex-A9 MPCore processors in the Zynq SoC and MPSoC). It’s complicated.

The rule that we typically apply in the company is that if you have to FedEx it, it’s hardware; if you can email it, it’s software.

Now, what’s very important about the Ross Freeman Award for Technical Innovation is that the winners are selected by their technical peers at Xilinx. So in the end, the award decision rests not with a small group of Xilinx executives meeting in conclave. The executives select the finalists from nominations made by the Xilinx technical community, so getting nominated as one of the three top hardware or three top software innovations is an honor and recognition in itself.

It’s the Xilinx technical community that selects the award winners. I feel this is an important aspect of the award. Your peers are voting.

We have gone on a very long trajectory from introducing SerDes technology into our FPGAs [in the early 2000s] to today, when we have world-leading SerDes technology. This year’s Ross Freeman Award for Technical Innovation in hardware went to the GTY SerDes technology used in our 20nm Virtex UltraScale device family. That’s a SerDes that goes up to 30.5Gbps. Occasionally, you’ll read about other products that have this kind of capability, but the GTY SerDes technology is a big deal because it spans a huge range—500Mbps to 30.5Gbps. The dynamic range is humongous.

2015 Ross Freeman Award for Technical Innovation, Hardware

The other aspect is the programmability of the Xilinx GTY SerDes. One of its key features is the fractional PLL. With one clock, you can program the GTY SerDes hardware to operate over a range of data rates. This capability avoids a lot ofexternal hardware to handle different data rates and can reduce the cost of a system very substantially

The other thing is that the GTY SerDes achieves these data rates in real designs, on real boards, plugged into real backplanes. Our customers may have to deal with backplanes that are pretty ugly (electrically speaking) and not under their control. Their new line card designs must plug in and work with existing system infrastructure. For that purpose a lot of smart and adaptive functionality is added to the transceiver to achieve high data rates in even harsh conditions

In addition, these GTY SerDes ports operate while surrounded by a few billion digital transistors switching on the same chip at hundreds of MHz. Implementing tens of these robust, programmable GTY SerDes ports implemented with a digital 20nm CMOS process on one chip with reasonable power dissipation and huge dynamic range while handling tremendous data rates is a unique engineering achievement.