XILINX FPGA (天津)技术研讨会邀请函

时间表

内容

13:30-15:00

Topic: Essentials of FPGA Design
Agenda
Basic FPGA Architecture
Xilinx Tool Flow
Lab 1: Xilinx Tool Flow
Reading Reports
Lab 2: Clocking Wizard and Pin Assignment
Lab 3: Pre-Assigning I/O Pins Using the I/O Planner
Global Timing Constraints
Lab 4: Global Timing Constraints
Synchronous Design Techniques

时间表

内容

15:10-16:20

Topic: On-Chip FPGA Debugging Using ChipScope Pro
Agenda
Overview and Xilinx Development Tools Review
How the ChipScope Pro Tool Works
Inserting the Cores
Triggering and Storage
Visualizing Data – The ChipScope Pro Analyzer Tool
Understanding the Design
Lab 1: Using the Inserter Tool from Project Navigator
Lab 2: Using the Inserter Tool from the PlanAhead Software
Adding a VIO Core – The CORE Generator Tool Flow
Lab 3: Using the CORE Generator Tool from Project Navigator
More on Triggering and Storage
Tips, Tricks and Timing
Lab 4: Debug a broken design

16:30-17:30

Topic: Designing with the Spartan-6 Memory Controller Block
Agenda
The Spartan-6 Memory Controller Block
Lab 1 – Generate the default MIG design: Traffic Generator
Understanding the Traffic Generator Example
User Interface Basics
Lab 2 – Modify/Sim/Build the default MIG design: Traffic Generator
Hardware Debug
Lab 3 – Download and Debug
User Interface Design
Lab 4 – Design New User Logic

17:30-18:00

Xilinx 7 Series update