Luke Miller并非一开始就是HLS(高层次综合)的倡导者。在使用早期的工具版本的时候,他似乎有过一些糟
FPGA专家教您如何在FPGA设计中使用HLS
作者: Steve Leibson,赛灵思战略营销与商业规划总监
SemiWiki 有了一位新的博主,被称为“The FPGA
Expert(FPGA专家)”。通过LinkedIn简单搜索,我得知这位FPGA专家是Luke
Miller,他最近发表了一篇博文,介绍如何使用高层次综合(HLS)开发从C到其他HLL版本的各种加
Miller曾经在IBM公司担任过ASIC设计师,在Lockheed担任过硬件师(工程师/架构师),
“设计时间的加速并非从C到VHDL的转换, 真正起到关键因素的是仿真域 —您再也无需通过RTL逐件验证每项设计。”
Luke Miller并非一直都是HLS(高层次综合)的倡导者。在使用早期的工具版本的时候,他似乎有些糟糕的经
点击此处,阅读Miller有关HLS的建议:“高层次综合 —它真的行! ( High Level Synthesis – It’s for Real) ”http://www.semiwiki.com/forum/content/2222-high-le
下面是Miller的全文供参考:
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High Level Synthesis – It’s for Real
by
Published on 04-11-2013 06:30 PM
It was spring 2010 and I was asked to attend an HLS (High Level
Synthesis) meeting. To be honest I cringed, after my bad relationship
with Accel DSP and broken promises my heart was all walled up and needed
counseling. But my management had a way of making me an offer I could
not refuse, like keeping my job. So reluctantly I went. Does your
employer do lunch and learns instead of real training? You know what
that equals right? A 1/8 pay cut, but let’s play nice.
Anyways
after the usual introductions at the meeting they began to get into the
meat of the tool. I quickly diverted and asked if we could see the tool
in action and move away from the power point and boy did they. First up
was a cookie cutter FIR filter but it worked, really! Then they moved
into floating point designs etc. This HLS was the greatest thing since
sliced bread. I saw its potential and I needed to try it. We all agreed
on an evaluation period. Now I am by no means the best coder in the
world, but even the best would have a hard time beating the HLS tool
with respect to design time, area and latency.
What HLS is not:
It is not a coder in a box, thus sit down the software guy and have him
designing FPGAs. You need to understand the FPGA, no exceptions or you
will have a fat, slow design. The C or its variant will need to be
restructured, smartly, thus helping the tool out so it can perform
better. It is not a button you press and you have a bit image. I know
how program managers think.
I leverage HLS tools in this fashion. I view it as Xilinx Corgen
on steroids which are driven by a C file. The speed up in design time
is not in the translation from C to VHDL but really is in the simulation
domain. You are no longer verifying designs piece by piece using RTL.
For example, I design a Beamfomer in C. I compile it and then run
‘a.exe’ and verify that the answer matches the expects. That took about a
second. For many PRIs of data that could of taken hours in ModelSim.
Catching on? I then bring up the HLS tool and pull in the C file and the
tool reports the latency, area, clock frequency etc. From that
information I can determine which FPGA to use. I then start using
directives to optimize the area / latency by using unrolls and pipeline
directives. About an hour later my beamformer is done. I then simulate
the RTL at my top level but I already know the math works and the tool
took care of the boundary conditions. The goal of this article is by no
means a recipe on HLS usage but hopefully entices you to check it out,
you won’t be sorry.
本视频基于Xilinx公司的Artix-7FPGA器件以及各种丰富的入门和进阶外设,提供了一些典型的工程实例,帮助读者从FPGA基础知识、逻辑设计概念
本课程为“从零开始大战FPGA”系列课程的基础篇。课程通俗易懂、逻辑性强、示例丰富,课程中尤其强调在设计过程中对“时序”和“逻辑”的把控,以及硬件描述语言与硬件电路相对应的“
课程中首先会给大家讲解在企业中一般数字电路从算法到流片这整个过程中会涉及到哪些流程,都分别使用什么工具,以及其中每个流程都分别做了
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