Adam Taylor玩转MicroZed系列第85 部分: SDSoC之一—首次安装

Adam Taylor玩转MicroZed系列第85 部分: SDSoC之一—首次安装

By Adam Taylor

When you stop and look at the history of FPGA development techniques since FPGA’s were first introduced in the mid-1980s, there has been an increasing trend to develop at a higher abstraction level; the new Xilinx SDSoC development environment continues this trend.

At first, FPGAs were developed schematically using standard logic gates and flip flops to implement required functions within the device. However this approach has several severe limitations when it comes to describing large designs and complex functionality, and for verification. It is much easier to describe the functionality you require at a higher level and allow the tool chain to determine the gate-level implementation. This is where Hardware Description Languages like Verilog and VHDL introduced a great advantage as they allowed us to program at a higher abstraction level where we describe the behavior we want to implement and the synthesis tools determine the actual logic.

Of course with HDLs we must code in specific ways and with constraints on supported commands if we wish the code to be synthesisable (although this does not apply for verification). As a result, much HDL development is performed at the Register Transfer Level (RTL). While HDLs have been the mainstay for a large number of years, increasing device capabilities, size, and performance mean that development of designs based on FPGAs and programmable SoCs using an HDL now faces the same issues schematic design did.

This all gets further complicated when we add SoCs like the Zynq into consideration. We want to ensure that we can maximize SoC performance by accelerating functions within the PL (programmable logic) side of the device. However we may not know until we are advanced in development if we have chosen all of the right functions for acceleration. Changes at a later stage will require further (unwelcome and potentially expensive) development time.

SDSoC enables us to not only significantly increase the level of abstraction as it builds upon the code generated by Vivado HLS but it also creates a tightly integrated development environment, which also allows us to effectively design the SoC application and achieve our system performance targets by accelerating selected functions within the device’s PL side. Moving functions into the PL from the PS (processor system) is very simple to do with the SDSoC development environment once we have determined which ones we wish to move. Then the build process creates the boot image in a single click.

Slick. Very slick.

Over the next few weeks, I am going to focus on SDSoC in this blog as we explore how it functions, how we can use it, and how it allows us to develop applications in C or C++ for our Zynq design.

As always with this blog, the best place to start is to provide a very simple overview of how the tool works. One of the first things I noticed when I opened the tool is that it is Eclipse-based and looks very familiar to the SDK we have been using to develop our SW applications to date.

SDK SoC Welcome Page

SDSoC Development environment

However, while similar there are a number of differences that we’ll explore in detail. At the very top level overview of SDSoC is as functions as follows:

1. We develop our application in C or C++
2. We profile the application to determine the performance bottle necks
3. Using the profiling information we can identify functions to accelerate within the PL side of the device
4. We can then build the system and generate the SD card image
5. Once the hardware is on the board we can undertake analyse the performance further and optimise the acceleration functions as required

When we use SDSoC, we can chose either a bare-metal, FreeRTOS, or Linux operating system and SDSoC includes support for most of the Zynq development boards including the Zed, Avnet MicroZed, and Digilent Zybo.

This gives us a lot of very exciting things to look at over the upcoming weeks.

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