请教一个verilog问题,谢谢!

发布: 2017-2-18 00:05 | 作者: qwer20 | 来源: EETOP 赛灵思(Xilinx) 社区

CODE:

`ifdef D3D_SYNC_RESET always @(posedge clk_core) begin `else always @(posedge clk_core or negedge rst_x) begin `endif if (rst_x == `D3D_RESET_POL) begin r_state <= IDLE; end else begin case (r_state) IDLE: begin if (i_en) r_state <= LINE_0; end LINE_0: begin if (i | w_reject_l0) r_state <= LINE_1; end LINE_1: begin if (i | w_reject_l1) r_state <= LINE_2; end LINE_2: begin if (i | w_reject_l2) r_state <= IDLE; end endcase end end请教下,这个里面的`ifdef,他是到`endif结束呢?还是把下面状态机运行完呢?假设D3D_SYNC_RESET已定义。谢谢!
woai2020 (2017-2-18 09:35:24)
回复 1# qwer20 ifdef与c语言中的含义一样,这里你假设D3D_SYNC_RESET已定义那么代码将变成 always @(posedge clk_core) begin if (rst_x == `D3D_RESET_POL) begin r_state <= IDLE; end else begin case (r_state) IDLE: begin if (i_en) r_state <= LINE_0; end LINE_0: begin if (i | w_reject_l0) r_state <= LINE_1; end LINE_1: begin if (i | w_reject_l1) r_state <= LINE_2; end LINE_2: begin if (i | w_reject_l2) r_state <= IDLE; end endcase end end 而不是你想的状态机运不运行的问题,与这个无关
qwer20 (2017-2-18 19:09:03)
回复 2# woai2020 懂了,谢谢!

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