how to change VHDL code to get rid of latch's

发布: 2017-6-25 13:41 | 作者: xiaoyisimonguo | 来源: EETOP 赛灵思(Xilinx) 社区

please help, I need to change the following code to get rid of the latch synthesized clk_en_latch: PROCESS(clk_enable, clk) BEGIN IF clk = '0' THEN latched_clk_en <= clk_enable; END IF; END PROCESS; many thanks