help on DC timing violation

发布: 2017-6-30 13:22 | 作者: xiaoyisimonguo | 来源: EETOP 赛灵思(Xilinx) 社区

DC reported a -1,18 slack of setup violation:the data arrive path is like this: [url=pin#ORCA]I_ORCA_TOP/I_SDRAM_IF/sd_DQ_en[1][/url] (SDRAM_IF_sd_a_width10_sd_dq_width16) 0.00 0.34 r [url=pin#ORCA]I_ORCA_TOP/I_SDRAM_IF/sd_DQ_en[1][/url] (SDRAM_IF_sd_a_width10_sd_dq_width16) 0.00 0.34 r [url=pin#ORCA]I_ORCA_TOP/sd_DQ_en[1][/url] (ORCA_TOP_sd_a_width10_sd_dq_width16_sd_rfifo_depth64_sd_wfifo_depth64_pci_data_width16_pci_rfifo_depth32_pci_wfifo_depth32) 0.00 0.34 r [url=pin#ORCA]I_ORCA_TOP/sd_DQ_en[1][/url] (ORCA_TOP_sd_a_width10_sd_dq_width16_sd_rfifo_depth64_sd_wfifo_depth64_pci_data_width16_pci_rfifo_depth32_pci_wfifo_depth32) 0.00 0.34 r [url=pin#ORCA]U14/I[/url] (invbd7) 0.00 0.34 r [url=pin#ORCA]U14/ZN[/url] (invbd7) 0.07 0.41 f [url=pin#ORCA]U15/I[/url] (invbdk) 0.00 0.41 f [url=pin#ORCA]U15/ZN[/url] (invbdk) 0.27 0.68 r [url=pin#ORCA]sdram_DQ_iopad_1/OEN[/url] (pc3b05) 0.01 0.69 r [url=pin#ORCA]sdram_DQ_iopad_1/PAD[/url] (pc3b05) 3.33 4.02 rWarning: Can't find object '.' in design 'ORCA'. (UID-95) [url=port#ORCA]sd_DQ[1][/url] () 0.16 4.18 r data arrival time 4.18 Please note the two numbers in red, 0.69 and 3.33, they are the transitions, Rising on OEN, and Rising on PADwe all know the OEN, aka, output enable pin for PAD cell, and it is active low, meaning rising on OEN would disable the outputpath, so Rising on PAD would not be caused by OEN Rising, the path does not exist Please help to solve the issue, may be declare false path? Don't the io library provide the information? please help